
SGNT Technologies Inc. provides cost effective VLSI and Board
level hardware design services. In one area of VLSI ASIC design where
SGNT can provide a very effective service is DFT consultancy. Instead of
employing a full-time designer for DFT work, the clients may hire
outsourced consultants to perform this work for a certain period at
various stages of the ASIC design. SGNT has consultants with twenty
years of experience in DFT design for VLSI ASIC’s with 10+ million
gates. We can provide services at the following areas of VLSI ASIC
design.
RTL AND BLOCK LEVEL:
| IP core - Integrate IP core’s scan and test architecture with the rest of ASIC to implement: | |
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| Customer blocks - Architect Scan methodology to provide: | |
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| Modify RTL for each block for DFT compliance (clock gating logic, asynchronous reset etc.). | |
| Ensure that each block level test coverage is >99%. | |
| Generate fault coverage report for each block |
CHIP LEVEL:
| Ensure all testability hooks are accessible from chip I/O. | |
| Design JTAG compliant test controller to implement - Boundary Scan, Memory | |
| BIST, XOR-tree, IDDQ testing, and other user specific test features. | |
| Scan testing - external or built-in. | |
| Generate chip level Scan ATPG test vectors | |
| Support static timing analysis closure in various test modes by writing scripts, e.g. TCL for Primetime. |
We can also provide support for production testing of ASIC’s with IC testers (e.g. Teradyne, Agilent etc.):
| Generate production worthy Scan test vectors for IC testers. | |
| Generate functional test vectors for IC testing. | |
| Support failure analysis and yield improvement with Scan test vectors. |
ASIC DESIGN FOR TESTING (DFT)
A typical ASIC design flow showing areas with SGNT DFT support is given below.

DFT is an essential part of ASIC design. Design houses require
excellent DFT expertise on “as needed” basis to cut cost. SGNT provides
superior DFT services utilizing its in-house experts to achieve rapid
time-to-market and ROI objectives.